Here is a short report on the current state of my MC1 project, which is an SoC design for FPGA:s. The MC1 is a custom computer that is mainly used for testing and proving the MRISC32 ISA. Currently the main features of the computer are: It is based around the MRISC32-A1 soft CPU, running at …
Ideas for MRISC32 vector operations
This time I want to talk about some future directions for the MRISC32 vector model. For a recap, see: The MRISC32 – A vector first CPU design. The vector model that was chosen for the MRISC32 instruction set architecture has already proven itself successful. Since it has been implemented in the single-issue, in-order CPU MRISC32-A1, …
MRISC32 conditional moves
I recently implemented support for conditional move (or more precisely, conditional select) for the MRISC32 ISA, and I wanted to share some thoughts on that. It’s one of those pieces that just fit into the MRISC32 ISA puzzle very nicely. The problems with branches In any pipelined CPU architecture, one of the biggest problems is …
IEEE 754 suggestion: A “core” subset
UPDATE (2020-01-11): A more detailed specification can be found here: LeanFloat (GitHub). I’ve been developing software for over 30 years, and during those years I have frequently come across problems relating to a few features of the IEEE 754 floating point standard, namely: Denormalized numbers Configurable rounding modes Recently I have also developed a custom …
Some features of the MRISC32 ISA
In my previous post, The MRISC32 – A vector first CPU design, I went through some of the principles of the MRISC32 ISA. In this post I’d like to focus on scalar operations and present some of the features that set the ISA apart from others. I have recently made some progress with a GCC …
The MRISC32 – A vector first CPU design
Edit: There is now an MRISC32 homepage. For some time now I have been working on my first CPU design as a hobby project. It started with a desire to learn more about CPU architecture design, and in particular instruction set architecture (ISA) design. To be clear, I’m not a hardware or CPU designer by …
Installing Intel/Altera Quartus Prime in Ubuntu 17.10
UPDATE: The new Intel® Quartus® Prime Lite 18.1 installs without any problems under Ubuntu 18.04 (LTS). Hopefully this article is now superfluous (unless you need to install older version of Quartus onto older versions of Ubuntu). Installing the Intel® Quartus® Prime Lite edition software (the free Intel/Altera FPGA design software suite) for Ubuntu 17.10 is …
Benchmarking OS primitives
Lately I have taken some interest in the hardware and software of C++ build servers. One of the things that I have noticed is that there is a significant performance difference between Windows and Linux machines for common build tasks, such as cloning a git repository, running CMake and caching build results. Some of these differences …
Faster C++ builds
The C++ language is known for its long compilation times. While that is largely true (compared to many other languages), C++ is also one of the most mature languages out there, with rich tool support. There are now a lot of tools and good practices that can be applied to most C++ projects to help …
A stable mainline branching model for Git
In this article I will describe a Git workflow and branching model that I have used successfully in several projects and companies for many years now. It scales from small to large teams, and it fixes some common problems with Continuous Integration and GitFlow, for instance. Moreover, it is very simple and results in a nice Git …