This is a quick introduction to software development for the MRISC32 architecture. The MRISC32 architecture is a novel 32-bit Vector/RISC instruction set architecture, designed to be efficient, powerful, forward looking and easy to work with. It is also open and completely free for anyone to use as they wish. The compiler For compiling programs there …
I want to show a thing (C++ to machine code)
If you are like me and spend a lot of time looking at assembly language output from compilers, this article may not provide much new information. If not, however, you will hopefully find it interesting. The thing I want to show is how seemingly lengthy and complex C++ code can be compiled into very compact …
Three fundamental flaws of SIMD ISA:s
According to Flynn’s taxonomy SIMD refers to a computer architecture that can process multiple data streams with a single instruction (i.e. “Single Instruction stream, Multiple Data streams”). There are different taxonomies, and within those several different sub-categories and architectures that classify as “SIMD”. In this post, however, I refer to packed SIMD ISA:s, i.e. the …
MRISC32 – Stabilizing the Base architecture
The MRISC32 instruction set architecture recently reached a seemingly insignificant but major milestone: As of version 0.2 of the ISA the key elements of the Base architecture have been fixed, and it is very unlikely that any changes will be made to it any time soon. Base architecture? “Base architecture?” you say. I’m glad you …
MC1: A custom computer with a custom CPU based on a custom ISA
Here is a short report on the current state of my MC1 project, which is an SoC design for FPGA:s. The MC1 is a custom computer that is mainly used for testing and proving the MRISC32 ISA. Currently the main features of the computer are: It is based around the MRISC32-A1 soft CPU, running at …
Ideas for MRISC32 vector operations
This time I want to talk about some future directions for the MRISC32 vector model. For a recap, see: The MRISC32 – A vector first CPU design. The vector model that was chosen for the MRISC32 instruction set architecture has already proven itself successful. Since it has been implemented in the single-issue, in-order CPU MRISC32-A1, …
MRISC32 conditional moves
I recently implemented support for conditional move (or more precisely, conditional select) for the MRISC32 ISA, and I wanted to share some thoughts on that. It’s one of those pieces that just fit into the MRISC32 ISA puzzle very nicely.
IEEE 754 suggestion: A “core” subset
I’ve been developing software for over 30 years, and during those years I have frequently come across problems relating to a few features of the IEEE 754 floating point standard, namely: Denormalized numbers Configurable rounding modes Recently I have also developed a custom CPU (MRISC32), and when doing the hardware implementation of the floating point …
Some features of the MRISC32 ISA
In my previous post, The MRISC32 – A vector first CPU design, I went through some of the principles of the MRISC32 ISA. In this post I’d like to focus on scalar operations and present some of the features that set the ISA apart from others. I have recently made some progress with a GCC …
The MRISC32 – A vector first CPU design
For some time now I have been working on my first CPU design as a hobby project. It started with a desire to learn more about CPU architecture design, and in particular instruction set architecture (ISA) design. To be clear, I’m not a hardware or CPU designer by trade, but I have worked with performance …