If you are like me and spend a lot of time looking at assembly language output from compilers, this article may not provide much new information. If not, however, you will hopefully find it interesting. The thing I want to show is how seemingly lengthy and complex C++ code can be compiled into very compact …
Three fundamental flaws of SIMD ISA:s
According to Flynn’s taxonomy SIMD refers to a computer architecture that can process multiple data streams with a single instruction (i.e. “Single Instruction stream, Multiple Data streams”). There are different taxonomies, and within those several different sub-categories and architectures that classify as “SIMD”. In this post, however, I refer to packed SIMD ISA:s, i.e. the …
MRISC32 – Stabilizing the Base architecture
The MRISC32 instruction set architecture recently reached a seemingly insignificant but major milestone: As of version 0.2 of the ISA the key elements of the Base architecture have been fixed, and it is very unlikely that any changes will be made to it any time soon. Base architecture? “Base architecture?” you say. I’m glad you …
MC1: A custom computer with a custom CPU based on a custom ISA
Here is a short report on the current state of my MC1 project, which is an SoC design for FPGA:s. The MC1 is a custom computer that is mainly used for testing and proving the MRISC32 ISA. Currently the main features of the computer are: It is based around the MRISC32-A1 soft CPU, running at …
Ideas for MRISC32 vector operations
Edit: Some parts of the ISA have changed since this article was written (e.g. register names). See the latest MRISC32 Instruction Set Manual. This time I want to talk about some future directions for the MRISC32 vector model. For a recap, see: The MRISC32 – A vector first CPU design. The vector model that was …
MRISC32 conditional moves
Edit: Some parts of the ISA have changed since this article was written (e.g. register names). See the latest MRISC32 Instruction Set Manual. I recently implemented support for conditional move (or more precisely, conditional select) for the MRISC32 ISA, and I wanted to share some thoughts on that. It’s one of those pieces that just …
IEEE 754 suggestion: A “core” subset
UPDATE (2020-01-11): A more detailed specification can be found here: LeanFloat (GitHub). I’ve been developing software for over 30 years, and during those years I have frequently come across problems relating to a few features of the IEEE 754 floating point standard, namely: Denormalized numbers Configurable rounding modes Recently I have also developed a custom …
Some features of the MRISC32 ISA
Edit: Some parts of the ISA have changed since this article was written (e.g. register names). See the latest MRISC32 Instruction Set Manual. In my previous post, The MRISC32 – A vector first CPU design, I went through some of the principles of the MRISC32 ISA. In this post I’d like to focus on scalar …
The MRISC32 – A vector first CPU design
Edit: There is now an MRISC32 homepage. Also, some parts of the ISA have changed since this article was written (e.g. register names). See the latest MRISC32 Instruction Set Manual. For some time now I have been working on my first CPU design as a hobby project. It started with a desire to learn more …
Installing Intel/Altera Quartus Prime in Ubuntu 17.10
UPDATE: The new Intel® Quartus® Prime Lite 18.1 installs without any problems under Ubuntu 18.04 (LTS). Hopefully this article is now superfluous (unless you need to install older version of Quartus onto older versions of Ubuntu). Installing the Intel® Quartus® Prime Lite edition software (the free Intel/Altera FPGA design software suite) for Ubuntu 17.10 is …