The MRISC32 instruction set architecture recently reached a seemingly insignificant but major milestone: As of version 0.2 of the ISA the key elements of the Base architecture have been fixed, and it is very unlikely that any changes will be made to it any time soon. Base architecture? “Base architecture?” you say. I’m glad you …

Edit: Some parts of the ISA have changed since this article was written (e.g. register names). See the latest MRISC32 Instruction Set Manual. This time I want to talk about some future directions for the MRISC32 vector model. For a recap, see: The MRISC32 – A vector first CPU design. The vector model that was …

Edit: Some parts of the ISA have changed since this article was written (e.g. register names). See the latest MRISC32 Instruction Set Manual. I recently implemented support for conditional move (or more precisely, conditional select) for the MRISC32 ISA, and I wanted to share some thoughts on that. It’s one of those pieces that just …

Edit: Some parts of the ISA have changed since this article was written (e.g. register names). See the latest MRISC32 Instruction Set Manual. In my previous post, The MRISC32 – A vector first CPU design, I went through some of the principles of the MRISC32 ISA. In this post I’d like to focus on scalar …

Edit: There is now an MRISC32 homepage. Also, some parts of the ISA have changed since this article was written (e.g. register names). See the latest MRISC32 Instruction Set Manual. For some time now I have been working on my first CPU design as a hobby project. It started with a desire to learn more …